US 12,347,502 B2
Page buffer, memory device including page buffer and memory system including memory device
Kang Woo Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 22, 2023, as Appl. No. 18/321,576.
Claims priority of application No. 10-2022-0164302 (KR), filed on Nov. 30, 2022.
Prior Publication US 2024/0177786 A1, May 30, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A memory device, comprising:
first memory cells, each configured to be programmed to have a threshold voltage corresponding to any one of a plurality of program states;
data latches configured to respectively store a plurality of pieces of first logical page data to be stored in the first memory cells; and
a pre-sensing latch configured to store data sensed through a pre-verify operation,
wherein the pre-sensing latch stores second logical page data to be stored in second memory cells when a main verify operation for a threshold program state, among the plurality of program states, has passed.