| CPC G11C 16/0483 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 23 Claims |

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1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a first three-dimensional memory array located in a first memory array region; and
a second three-dimensional memory array located in a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by an inter-array region, wherein the electrically conductive layers comprise common word lines for the first three-dimensional memory array and for the second three-dimensional memory array,
wherein:
the alternating stack is laterally bounded by two trench fill structures that are laterally space apart along a second horizontal direction by an inter-trench spacing;
the electrically conductive layers continuously extend between the first memory array region and the second memory array region and comprise a respective bridge region that is located in the inter-array region and having a width along the second horizontal direction that is less than the inter-trench spacing;
the inter-array region comprises a stepped surface region comprising first vertically-extending surface segments of the alternating stack that are perpendicular to the first horizontal direction and second vertically-extending surface segments of the alternating stack that are perpendicular to the second horizontal direction; and
a first plurality of second vertically-extending surface segments is laterally offset from one of the trench fill structures by a same lateral spacing.
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