US 12,347,490 B2
Compact k-XOR-SAT filtering with cams
Giacomo Pedretti, Milan (IT); Todd Richmond, Ft. Collins, CO (US); and Thomas Van Vaerenbergh, Flemish Brabant (BE)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed by HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP, Spring, TX (US)
Filed on Aug. 10, 2023, as Appl. No. 18/447,776.
Prior Publication US 2025/0054547 A1, Feb. 13, 2025
Int. Cl. G11C 15/04 (2006.01); H03K 19/21 (2006.01)
CPC G11C 15/046 (2013.01) [H03K 19/21 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a row of content addressable memory (CAM) cells programmed to store a k-exclusive OR-satisfaction (k-XOR-SAT) clause of a Boolean satisfiability problem;
a sense amplifier that, in response to an input vector being applied to the row of CAM cells:
compares, at k discrete times, voltage output of a match line associated with the row of CAM cells to a threshold voltage, wherein k represents a number of literals of the k-XOR-SAT clause;
a counter circuit that counts a number of matches returned by the match line based on the k voltage comparisons of the sense amplifier; and
a logic circuit that outputs a signal indicating the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a pre-determined parity condition.