US 12,347,484 B2
Memory device of non-volatile memory cells
Hieu Van Tran, San Jose, CA (US); Nhan Do, Saratoga, CA (US); Farnood Merrikh Bayat, Goleta, CA (US); Xinjie Guo, Goleta, CA (US); Dmitri Strukov, Goleta, CA (US); Vipin Tiwari, Dublin, CA (US); and Mark Reiten, Alamo, CA (US)
Assigned to Silicon Storage Technology, Inc., San Jose, CA (US); and The Regents of the University of California, Oakland, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US); and The Regents of the University of California, Oakland, CA (US)
Filed on Apr. 28, 2023, as Appl. No. 18/141,090.
Application 18/141,090 is a continuation of application No. 17/580,862, filed on Jan. 21, 2022, granted, now 12,300,313.
Application 17/580,862 is a continuation of application No. 15/594,439, filed on May 12, 2017, granted, now 11,308,383, issued on Apr. 19, 2022.
Claims priority of provisional application 62/337,760, filed on May 17, 2016.
Prior Publication US 2023/0259738 A1, Aug. 17, 2023
Int. Cl. G11C 11/54 (2006.01); G06F 3/06 (2006.01); G06N 3/04 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 29/38 (2006.01)
CPC G11C 11/54 (2013.01) [G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G06N 3/04 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/16 (2013.01); G11C 16/3436 (2013.01); G11C 29/38 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of non-volatile memory cells arranged in rows and columns, having source regions arranged in rows and columns, and drain regions arranged in rows and columns, wherein respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other;
respective ones of the plurality of non-volatile memory cells comprise:
a channel region extending between one of the source regions and one of the drain regions,
a floating gate disposed over and insulated from a first portion of the channel region, and
a first non-floating gate disposed over and insulated from a second portion of the channel region;
a plurality of first lines, wherein respective ones of the plurality of first lines electrically connect together the source regions in one of the rows of the source regions and are physically isolated from the source regions in other rows of the source regions;
a plurality of second lines, wherein respective ones of the plurality of second lines electrically connect together the first drain regions of one of the columns of drain regions and are physically isolated from the second drain regions of the one column of drain regions;
a plurality of third lines, wherein respective ones of the plurality of third lines electrically connect together the second drain regions of one of the columns of drain regions and are physically isolated from the first drain regions of the one column of drain regions;
a plurality of fourth lines, wherein respective ones of the plurality of fourth lines electrically connect together the first non-floating gates of odd row memory cells in one of the columns of the memory cells and are physically isolated from the first non-floating gates of even row memory cells in the one column of the memory cells; and
a plurality of fifth lines, wherein respective ones of the plurality of fifth lines electrically connect together the first non-floating gates of even row memory cells in one of the columns of the memory cells and are physically isolated from the first non-floating gates of odd row memory cells in the one column of the memory cells.