US 12,347,482 B2
Memory device including plurality of overlap memory cell arrays with folded bit-lines
Yuki Okamoto, Kanagawa (JP); and Tatsuya Onuki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Aug. 18, 2022, as Appl. No. 17/890,335.
Application 17/890,335 is a continuation of application No. 16/968,922, granted, now 11,423,975, previously published as PCT/IB2019/051135, filed on Feb. 13, 2019.
Claims priority of application No. 2018-030810 (JP), filed on Feb. 23, 2018; application No. 2018-056653 (JP), filed on Mar. 23, 2018; and application No. 2018-077326 (JP), filed on Apr. 13, 2018.
Prior Publication US 2022/0392521 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/4097 (2006.01); G11C 11/4091 (2006.01); H10D 30/67 (2025.01); H10D 62/80 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01)
CPC G11C 11/4097 (2013.01) [G11C 11/4091 (2013.01); H10D 30/6734 (2025.01); H10D 30/6755 (2025.01); H10D 62/80 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01)] 8 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first sense amplifier;
a second sense amplifier being adjacent to the first sense amplifier;
a first cell array comprising a plurality of first memory cells, the first cell array provided over the first sense amplifier and the second sense amplifier;
a second cell array comprising a plurality of second memory cells, the second cell array provided over the first cell array;
a first bit line and a second bit line each electrically connected to the first sense amplifier; and
a third bit line and a fourth bit line each electrically connected to the second sense amplifier,
wherein a region of the first cell array and a region of the second cell array overlap with each other,
wherein the region of the first cell array comprises:
a first group;
a second group being adjacent to the first group;
a third group being adjacent to the second group;
a fourth group being adjacent to the second group and the third group;
a fifth group being adjacent to the fourth group; and
a sixth group being adjacent to the fifth group,
wherein each of the first to sixth groups includes one or more first memory cells,
wherein the region of the second cell array comprises:
a seventh group;
an eighth group being adjacent to the seventh group;
a ninth group being adjacent to the eighth group;
a tenth group being adjacent to eighth group and the ninth group;
an eleventh group being adjacent to the tenth group; and
a twelfth group being adjacent to the eleventh group,
wherein each of the seventh to twelfth groups includes one or more second memory cells,
wherein the first bit line includes a first part electrically connected to the first group, a second part electrically connected to the third group, and a third part electrically connected to the ninth group,
wherein the second bit line includes a first part electrically connected to the second group, a second part electrically connected to the seventh group, and a third part electrically connected to the eighth group,
wherein the third bit line includes a first part electrically connected to the fourth group, a second part electrically connected to the sixth group, and a third part electrically connected to the twelfth group,
wherein the fourth bit line includes a first part electrically connected to the fifth group, a second part electrically connected to the tenth group, and a third part electrically connected to the eleventh group, and
wherein the first part of the third bit line is adjacent to the second part of the first bit line and the first part of the second bit line.