| CPC G11C 11/4096 (2013.01) [G11C 11/405 (2013.01); G11C 11/54 (2013.01); G11C 16/26 (2013.01)] | 10 Claims |
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1. A universal memory for In-Memory Computing (IMC), comprising:
at least one write word line;
at least one unit cell, including:
a write transistor, wherein a gate of the write transistor is connected to the write word line, and the write transistor is a transistor with adjustable threshold voltage; and
a read transistor, wherein a gate of the read transistor is connected to a drain or a source of the write transistor; and
at least one read word line, connected to a drain or a source of the read transistor;
wherein in a training mode, a storage potential of a storage node between the write transistor and the read transistor represents a weight of the unit cell;
in an inference mode, a threshold voltage of the write transistor represents the weight of the unit cell;
wherein a material of a channel layer of the write transistor is indium gallium zinc oxide (IGZO), indium oxide (In2O3), silicon (Si), germanium (Ge), or trivalent group-pentavalent group material.
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