| CPC G11C 11/406 (2013.01) [G06F 12/0223 (2013.01); G11C 11/40603 (2013.01); G11C 11/40611 (2013.01); G11C 11/40615 (2013.01); G11C 11/40618 (2013.01); G11C 11/408 (2013.01)] | 20 Claims |
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1. A semiconductor memory device, comprising:
a memory cell array having a plurality of rows of memory cells therein; and
a row hammer management circuit including a hammer address queue therein, the row hammer management circuit configured to:
receive first access row addresses from an external memory controller during a reference time interval;
store a first row address randomly selected from the first access row addresses in the hammer address queue, as a first candidate hammer address;
store a second row address received from the memory controller in the hammer address queue as a second candidate hammer address, in response to receiving a refresh management command from the memory controller; and
sequentially output candidate hammer addresses, which include the first candidate hammer address and the second candidate hammer address, as a hammer address; and
a refresh control circuit configured to: (i) receive the hammer address, and (ii) perform a hammer refresh operation on one or more victim rows of memory cells, which are physically adjacent to a row of memory cells that corresponds to the hammer address at at least a portion of first refresh timings based on a refresh command, and at a second refresh timing based on the refresh management command.
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