US 12,347,474 B2
Memory devices, circuits and methods of adjusting a sensing current for the memory device
Win-San Khwa, Taipei (TW); Jui-Jen Wu, Hsinchu (TW); Jen-Chieh Liu, Hsinchu (TW); and Meng-Fan Chang, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 6, 2024, as Appl. No. 18/434,752.
Application 18/434,752 is a continuation of application No. 17/577,040, filed on Jan. 17, 2022, granted, now 11,915,733.
Claims priority of provisional application 63/225,405, filed on Jul. 23, 2021.
Prior Publication US 2024/0177757 A1, May 30, 2024
Int. Cl. G11C 11/16 (2006.01); G11C 7/06 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01)
CPC G11C 11/1673 (2013.01) [G11C 11/161 (2013.01); G11C 7/06 (2013.01); G11C 7/062 (2013.01); G11C 11/1655 (2013.01); G11C 11/56 (2013.01); G11C 11/5607 (2013.01); G11C 13/0026 (2013.01); G11C 2013/0054 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a sense amplifier configured to output an output data in response to a cell current sensed from a bit line of a memory array and a reference current flowing from a reference array;
a first clamping circuit coupled between the sense amplifier and the memory array;
a second clamping circuit coupled between the sense amplifier and the reference array; and
a feedback circuit configured to determine whether the output data is a most significant bit (MSB) data to adjust the cell current or the reference current.