US 12,347,399 B2
Scanning signal line drive circuit and display device
Jun Nishimura, Kameyama (JP); Yoshihito Hara, Kameyama (JP); Masaki Maeda, Kameyama (JP); Yoshiharu Hirata, Kameyama (JP); Hideki Kitagawa, Kameyama (JP); Masamitsu Yamanaka, Kameyama (JP); and Tohru Daitoh, Kameyama (JP)
Assigned to Sharp Display Technology Corporation, Kameyama (JP)
Filed by Sharp Display Technology Corporation, Kameyama (JP)
Filed on Dec. 5, 2023, as Appl. No. 18/529,438.
Claims priority of application No. 2023-011531 (JP), filed on Jan. 30, 2023.
Prior Publication US 2024/0257774 A1, Aug. 1, 2024
Int. Cl. G09G 3/34 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/3446 (2013.01) [G11C 19/28 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display device comprising:
a scanning signal line drive circuit configured to drive a plurality of scanning signal lines, each connected to a plurality of pixel forming portions,
wherein the scanning signal line drive circuit includes a shift register having a plurality of stages corresponding to the plurality of scanning signal lines on a one-to-one basis and configured to operate based on a plurality of first clock signals and a plurality of second clock signals, each of the plurality of second clock signals having an amplitude that is greater than an amplitude of each of the plurality of first clock signals,
wherein a first unit circuit, among a plurality of unit circuits, that forms one of the plurality of stages included in the shift register includes;
a first output node configured to output a control signal for controlling an operation performed by a second unit circuit of the plurality of unit circuits,
a second output node configured to output a scanning signal to a corresponding one of the plurality of scanning signal lines,
a first control node configured to change from an off level to an on level based on a control signal output from a first output node of a third unit circuit of the plurality of unit circuits that forms a preceding stage,
a first output control transistor including a control terminal connected to the first control node, a first conduction terminal to which a corresponding one of the plurality of first clock signals is given, and a second conduction terminal connected to the first output node, and
a second output control transistor including a control terminal connected to the first control node, a first conduction terminal to which a corresponding one of the plurality of second clock signals is given, and a second conduction terminal connected to the second output node,
wherein a breakdown voltage of the second output control transistor is higher than a breakdown voltage of the first output control transistor, and
wherein a channel length of the second output control transistor is greater than a channel length of the first output control transistor.