| CPC G09G 3/3266 (2013.01) [G09G 3/3275 (2013.01); G09G 2300/0809 (2013.01); G09G 2320/0209 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/021 (2013.01)] | 23 Claims |
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1. A stage comprising:
a first input terminal;
a second input terminal configured to receive a first clock signal;
a third input terminal configured to receive a second clock signal;
an output terminal configured to output a gate signal;
an input part comprising a fourth transistor connected between the first input terminal and a first node, and comprising a gate electrode electrically connected to the second input terminal;
an output part comprising:
a seventh transistor connected between a first power line and the output terminal, and comprising a gate electrode electrically connected to a third node; and
an eighth transistor connected between a second power line and the output terminal, and comprising a gate electrode electrically connected to a fourth node;
a first signal-processing part comprising an eleventh transistor connected between the second power line and the fourth node, and comprising a gate electrode electrically connected to the first node; and
a second signal-processing part comprising a first transistor diode-connected between the third node and a sixth node, and comprising a gate electrode electrically connected to the sixth node.
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