| CPC G09G 3/3233 (2013.01) [G09G 3/3208 (2013.01); G09G 3/3258 (2013.01); G09G 2300/0804 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0204 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/043 (2013.01); G09G 2320/045 (2013.01)] | 20 Claims |

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1. A pixel circuit, comprising:
a driving circuit, a data writing circuit, a reset circuit, a light-emitting control circuit and a light-emitting element,
wherein the driving circuit comprises a control terminal, a first terminal and a second terminal, and the driving circuit is configured to control a driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light;
the light-emitting control circuit is connected to the first terminal of the driving circuit and a first voltage terminal, and is configured to apply a voltage of the first voltage terminal to the first terminal of the driving circuit in response to a light-emitting control signal;
a first terminal of the light-emitting element is configured to receive the driving current, and a second terminal of the light-emitting element is connected to a second voltage terminal;
an input terminal of the data writing circuit is connected to a data line, an output terminal of the data writing circuit is connected to a first node, and the data writing circuit is configured to apply a data voltage to the first node in response to a first control signal;
a first output terminal of the reset circuit is connected to the first node, and the reset circuit is configured to apply a reference voltage to the first node in response to a second control signal;
the pixel circuit further comprises a partition control circuit, the partition control circuit comprises a first terminal and a second terminal, the first terminal of the partition control circuit is connected to the first node, the second terminal of the partition control circuit is connected to the control terminal of the driving circuit, and the partition control circuit is configured to apply at least one of the data voltage and the reference voltage to the control terminal of the driving circuit in response to a partition control signal; and
a second output terminal of the reset circuit is connected to one of the first terminal and the second terminal of the driving circuit, and the reset circuit is further configured to apply an initialization voltage to one terminal, connected to the second output terminal, of the first terminal and the second terminal of the driving circuit in response to the partition control signal and a third control signal.
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