US 12,347,355 B2
Gate driving circuit and display panel
You Pan, Hubei (CN); Mang Zhao, Hubei (CN); and Qiang Gong, Hubei (CN)
Assigned to WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Hubei (CN)
Appl. No. 18/553,544
Filed by WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Hubei (CN)
PCT Filed Jul. 31, 2023, PCT No. PCT/CN2023/110172
§ 371(c)(1), (2) Date Sep. 29, 2023,
PCT Pub. No. WO2025/015634, PCT Pub. Date Jan. 23, 2025.
Claims priority of application No. 202310885898.4 (CN), filed on Jul. 18, 2023.
Prior Publication US 2025/0078710 A1, Mar. 6, 2025
Int. Cl. G09G 3/20 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/20 (2013.01) [G11C 19/287 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/04 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A gate driving circuit, comprising a plurality of gate driving units cascaded in a multi-stage series, each stage gate driving units comprising: a pull-up control module;
a pull-up node; a pull-down control module; a pull-down node; and
a pull-down module, wherein the pull-up control module is electrically connected to the pull-up node and configured to pull up a potential of the pull-up node; the pull-down control module which disconnects to the pull-up node, is electrically connected to the pull-down node, and is configured to pull down a potential of the pull-down node; and the pull-down module is electrically connected to the pull-up node and the pull-down node, and is configured to pull down the potential of the pull-up node under control of the potential of the pull-down node,
wherein the pull-down module comprises a fifth transistor;
a gate of the fifth transistor is electrically connected to the pull-down node, a first electrode of the fifth transistor is electrically connected to a reference low-level signal input terminal, and a second electrode of the fifth transistor is electrically connected to the pull-up node,
wherein the pull-down module further comprises a sixth transistor;
a gate of the sixth transistor is electrically connected to a scanning signal input terminal of a next one stage gate driving unit, a first electrode of the sixth transistor is electrically connected to a reference low-level signal input terminal, and a second electrode of the sixth transistor is electrically connected to the pull-up node, and
wherein the sixth transistor is provided in all stage gate driving units except a last stage gate driving unit.