US 12,347,354 B2
Shift register unit, method for driving the same, driving circuit and display device
Yingsong Xu, Beijing (CN); Zhenhua Zhang, Beijing (CN); Qian Ma, Beijing (CN); Xilei Cao, Beijing (CN); Changlong Yuan, Beijing (CN); Jingyi Feng, Beijing (CN); Weiyun Huang, Beijing (CN); and Benlian Wang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Jan. 25, 2024, as Appl. No. 18/423,236.
Application 18/423,236 is a continuation of application No. 17/598,790, granted, now 11,922,845, previously published as PCT/CN2020/123206, filed on Oct. 23, 2020.
Prior Publication US 2024/0161673 A1, May 16, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/20 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/20 (2013.01) [G11C 19/28 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/06 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A shift register unit, comprising a first node potential adjustment circuit, a first tank circuit, a second node control circuit, a second tank circuit, a third node control circuit, a first node control circuit and an output circuit, wherein
the first node control circuit is directly connected to an input terminal, a first clock signal terminal, a first isolation node, a fourth node, and a first voltage terminal, respectively;
the first node potential adjustment circuit is respectively directly connected to an adjustment clock signal terminal and a first node;
the first tank circuit is directly connected to the first node;
the third node control circuit is directly connected to the first clock signal terminal, a second clock signal terminal, the first isolation node, a third isolation node, the fourth node, the first voltage terminal, and a second voltage terminal, respectively;
the second node control circuit is directly connected to the first isolation node, the first voltage terminal, a second isolation node, a control clock signal terminal, and a third node, respectively;
the second tank circuit is configured to maintain a potential of the second node;
the output circuit is directly connected to the first node, the second voltage terminal, a driving voltage signal terminal, and a third voltage terminal, respectively; and
the first isolation node and the first node are the same node; or, the first isolation node and the first node are different nodes.