| CPC G09G 3/006 (2013.01) [G02F 1/13306 (2013.01); G09G 3/32 (2013.01); G09G 2310/0272 (2013.01); G09G 2330/021 (2013.01); G09G 2330/12 (2013.01); H01L 25/167 (2013.01)] | 20 Claims |

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1. A driver chip, comprising:
a logic control module;
at least one output pin electrically connected to the logic control module; and
a first functional pin electrically connected to the logic control module, wherein the first functional pin is capable of receiving a test signal, and the logic control module is configured to generate, according to the test signal, a test current flowing through each output pin;
an address pin electrically connected to the logic control module, wherein the address pin is capable of receiving driving data, and the driving data includes address verification information and a plurality of pieces of driving information corresponding to a plurality of driver chips that are cascaded; and the logic control module is further configured to:
obtain, according to the address verification information, a piece of driving information corresponding to the driver chip;
update the address verification information; and
generate driving data including updated address verification information; and
a relay pin electrically connected to the logic control module, wherein the relay pin is capable of outputting the driving data including the updated address verification information.
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