US 12,346,798 B2
Dynamic precision for neural network compute operations
Kamal Sinha, Rancho Cordova, CA (US); Balaji Vembu, Folsom, CA (US); Eriko Nurvitadhi, Hillsboro, OR (US); Nicolas C. Galoppo Von Borries, Portland, OR (US); Rajkishore Barik, Santa Clara, CA (US); Tsung-Han Lin, Campbell, CA (US); Joydeep Ray, Folsom, CA (US); Ping T. Tang, Edison, NJ (US); Michael S. Strickland, Sunnyvale, CA (US); Xiaoming Chen, Shanghai (CN); Anbang Yao, Beijing (CN); Tatiana Shpeisman, Menlo Park, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Altug Koker, El Dorado Hills, CA (US); Farshad Akhbari, Chandler, AZ (US); Narayan Srinivasa, Portland, OR (US); Feng Chen, Shanghai (CN); Dukhwan Kim, San Jose, CA (US); Nadathur Rajagopalan Satish, Santa Clara, CA (US); John C. Weast, Portland, OR (US); Mike B. MacPherson, Portland, OR (US); Linda L. Hurd, Cool, CA (US); Vasanth Ranganathan, El Dorado Hills, CA (US); and Sanjeev Jahagirdar, Folsom, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 12, 2023, as Appl. No. 18/351,124.
Application 18/351,124 is a continuation of application No. 17/317,857, filed on May 11, 2021, granted, now 11,748,606.
Application 17/317,857 is a continuation of application No. 15/495,020, filed on Apr. 24, 2017, granted, now 11,010,659, issued on May 18, 2021.
Prior Publication US 2024/0005136 A1, Jan. 4, 2024
Int. Cl. G06N 3/00 (2023.01); G06F 1/3287 (2019.01); G06F 1/3293 (2019.01); G06F 9/30 (2018.01); G06F 15/76 (2006.01); G06F 15/78 (2006.01); G06N 3/04 (2023.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G06N 3/084 (2023.01); G06T 1/20 (2006.01); G06T 15/00 (2011.01); G06T 1/60 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 1/3287 (2013.01); G06F 1/3293 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 15/76 (2013.01); G06F 15/78 (2013.01); G06N 3/04 (2013.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/08 (2013.01); G06N 3/084 (2013.01); G06T 1/20 (2013.01); G06T 15/005 (2013.01); G06T 1/60 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus comprising:
processor circuitry coupled to a memory, the processor circuitry to:
track precision level data relating to one or more neural network operations; and
expose the precision level data in one or more model specific registers, wherein the one or more model specific registers are used to tune one or more neural network applications executing on the processor circuitry.