US 12,346,790 B2
Methods and devices for programming a state machine engine
Harold B Noyes, Boise, ID (US); and David R. Brown, Lucas, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 15, 2023, as Appl. No. 18/110,162.
Application 18/110,162 is a continuation of application No. 16/715,755, filed on Dec. 16, 2019, granted, now 11,599,770.
Application 16/715,755 is a continuation of application No. 15/090,305, filed on Apr. 4, 2016, granted, now 10,509,995, issued on Dec. 17, 2019.
Application 15/090,305 is a continuation of application No. 13/552,492, filed on Jul. 18, 2012, granted, now 9,304,968, issued on Apr. 5, 2016.
Prior Publication US 2023/0196065 A1, Jun. 22, 2023
Int. Cl. G06N 3/04 (2023.01); G05B 19/045 (2006.01); G06F 9/448 (2018.01); G06F 15/78 (2006.01); G06N 3/02 (2006.01)
CPC G06N 3/04 (2013.01) [G05B 19/045 (2013.01); G06F 9/4498 (2018.02); G06F 15/7867 (2013.01); G06N 3/02 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a host processor configured to initiate transmission of data to be analyzed and configuration data;
a bus coupled to the host processor; and
a state machine engine coupled to the host processor via the bus to receive the configuration data and the data to be analyzed and to transmit a result of an analysis of the data to the host processor, wherein the state machine engine comprises:
a state machine lattice comprising a plurality of programmable elements, wherein each programmable element of the plurality of programmable elements comprises a programmable circuit element utilized in the analysis of the data;
a bus interface coupled to the bus and the state machine lattice and configured to receive the configuration data and the data to be analyzed, wherein the configuration data comprises initial state vector data to initially program the state machine lattice;
a data buffer coupled to the bus interface and the state machine lattice, wherein the bus interface is coupled to the state machine lattice via the data buffer, wherein the data buffer is configured to store the data to be analyzed to be transmitted to the state machine lattice; and
an inter-rank and processor buffer configured to:
receive the data to be analyzed and transmit the data to be analyzed to the state machine lattice; and
receive second data to be analyzed and transmit the second data to be analyzed to a second state machine lattice for analysis.