US 12,346,722 B2
Systems and methods for managing interrupt priority levels
Michael Catherwood, Tyler, TX (US); Howard Schlunder, Mesa, AZ (US); and David Mickey, Chandler, AZ (US)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Dec. 1, 2022, as Appl. No. 18/073,075.
Claims priority of provisional application 63/286,634, filed on Dec. 7, 2021.
Prior Publication US 2023/0176898 A1, Jun. 8, 2023
Int. Cl. G06F 9/48 (2006.01); G06F 8/71 (2018.01)
CPC G06F 9/4831 (2013.01) [G06F 8/71 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
non-transitory computer readable memory storing:
a current processor interrupt priority level;
a current disable interrupt control (DISICTL) interrupt priority level; and
a processor to:
update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions;
update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level; and
disable exceptions having a respective associated interrupt priority level equal to or lower than a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level during execution of respective code.