| CPC G06F 30/392 (2020.01) [H10D 89/10 (2025.01)] | 20 Claims |
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1. A method of arranging patterns of a semiconductor device, the method comprising:
generating a plurality of gate patterns corresponding to a set of gate structures of the semiconductor device and a plurality of conductive patterns corresponding to a set of metal diffusion (MD) conductive features of the semiconductor device, wherein each of the plurality of gate patterns and conductive patterns is located at a first horizontal level and extends along a first direction;
selecting one of the gate patterns as an input pin or one of the conductive patterns as an output pin; and
generating, based on a selected gate pattern or a selected conductive pattern, a plurality of metallization patterns corresponding to a set of first metallization layers of the semiconductor device, wherein each of the plurality of metallization patterns is located at a second horizontal level overlying the first horizontal level and extends along a second direction substantially perpendicular to the first direction.
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