| CPC G06F 30/331 (2020.01) | 20 Claims |
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1. A computer-implemented method for testing an integrated circuit design, the method comprising:
running a simulation that includes:
reading, by a controller model, controller instructions from a memory model;
executing, by the controller model, microcode to translate the controller instructions into device instructions for an integrated circuit design under test; and
dispatching, by the controller model, the device instructions onto a bus interface between the controller model and the integrated circuit design, wherein the device instructions are dispatched onto the bus interface with intervening idle cycles;
capturing bus interface activity on the bus interface to generate a stimulus file, wherein one or more of the intervening idle cycles are excluded from the stimulus file; and
executing a test bench driver to bypass the microcode and replay the simulation, wherein replaying the simulation includes:
reading, by the test bench driver, the stimulus file; and
injecting, by the test bench driver, the device instructions from the stimulus file into the integrated circuit design without the excluded one or more of the intervening idle cycles.
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