US 12,346,612 B2
Memory sub-system command fencing
Dhawal Bavishi, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 25, 2024, as Appl. No. 18/615,760.
Application 18/615,760 is a continuation of application No. 17/464,813, filed on Sep. 2, 2021, granted, now 11,941,291.
Prior Publication US 2024/0231703 A1, Jul. 11, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a first number of commands for execution on a memory sub-system;
receiving a second number of commands for execution on the memory sub-system;
receiving a memory fencing command associated with the first number of commands and the second number of commands; and
executing the first number of commands in any order and executing at least one of the second number of commands after execution of at least one of the first number of commands in response to receiving the memory fencing command, wherein the at least one of the first number of commands writes data to a first location in the memory sub-system and the at least one of the second number of commands reads the data from the first location in the memory sub-system.