US 12,346,608 B2
Asynchronous arbitration across clock domains for register writes in an integrated circuit chip
Srinivas Satish Babu Bamdhamravuri, Newbury Park, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Oct. 30, 2023, as Appl. No. 18/497,888.
Application 18/497,888 is a continuation of application No. 17/451,754, filed on Oct. 21, 2021, granted, now 11,829,640.
Claims priority of provisional application 63/198,564, filed on Oct. 27, 2020.
Prior Publication US 2024/0134574 A1, Apr. 25, 2024
Prior Publication US 2024/0231699 A9, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory module comprising:
one or more volatile memory devices; and
a command buffer coupled to the one or more volatile memory devices, wherein the command buffer is configured to:
receive in-band register access commands from a host via a first interface;
receive side-band register access commands from the host via a second interface;
arbitrate between the in-band register access commands and the side-band register access commands received via the first and second interfaces; and
perform, on a command buffer register, register access operations corresponding to the in-band register access commands and the side-band register access commands.