US 12,346,603 B2
Interface read after write
Yue Chan, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 11, 2024, as Appl. No. 18/410,175.
Application 18/410,175 is a continuation of application No. 16/928,564, filed on Jul. 14, 2020, granted, now 11,907,572.
Claims priority of provisional application 62/954,869, filed on Dec. 30, 2019.
Prior Publication US 2024/0152294 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory sub-system comprising:
a memory device;
a processing device coupled to the memory device and configured to control cache memory for the memory device to store data prior to storing the data on the memory device; and
an interface of the memory sub-system comprising error correction circuitry and a comparator, wherein the interface is coupled to the processing device and configured to:
receive a write command addressed to a first address, a read command addressed to a second address from a host, and data corresponding to the write command from the host;
responsive to determining that the first address matches the second address and that the write command was inserted into a command buffer of the interface prior to inserting the read command into the command buffer:
drop the read command and the second address from the command buffer by sending a signal from the comparator to the error correction circuitry to cause the error correction circuitry to mark the read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the read command responsive to the read command being marked by the error correction circuitry; and
provide the data to the host from a read buffer of the interface.