US 12,346,596 B2
Semiconductor memory device for performing program operation and method of operating the same
Hyung Jin Choi, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 20, 2022, as Appl. No. 17/970,212.
Claims priority of application No. 10-2022-0008445 (KR), filed on Jan. 20, 2022.
Prior Publication US 2023/0229344 A1, Jul. 20, 2023
Int. Cl. G11C 16/10 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 8/08 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3418 (2013.01); G11C 16/3427 (2013.01); G11C 8/08 (2013.01); G11C 16/08 (2013.01); G11C 16/30 (2013.01); G11C 16/3431 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array circuit including a plurality of word lines and a plurality of memory cells connected to each of the plurality of word lines; and
a word line driving circuit configured to apply a pulse of a program voltage to a selected word line of the plurality of the word lines in a program operation, to apply a pulse of a step pass voltage to at least one non-selected word line adjacent to the selected word line in the program operation, and to apply a pulse of a pass voltage to remaining non-selected word lines except for the at least one non-selected word line in the program operation,
wherein the at least one non-selected word line includes at least one first non-selected word line, and
the pulse of the step pass voltage applied to the at least one first non-selected word line is changed from a first voltage level higher than the pass voltage to a second voltage level lower than the first voltage level.