US 12,346,592 B2
Write throughput improvement of flash memory device
Madhu Yashwanth Boenapalli, Hyderabad (IN); Sai Praneeth Sreeram, Anantapur (IN); and Surendra Paravada, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 22, 2023, as Appl. No. 18/472,959.
Prior Publication US 2025/0103232 A1, Mar. 27, 2025
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0647 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0619 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7208 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A host device comprising:
a memory configured to store a logical-to-physical address mapping (L2P) table of a flash memory device; and
one or more processors coupled to the memory and configured to be coupled to the flash memory device, wherein the one or more processors are configured to:
determine whether a trigger condition is satisfied, the trigger condition associated with checking a distribution of write data that is written to the flash memory device; and
based on a determination that the trigger condition is satisfied:
send a first command to the flash memory device to enable a host write monitoring mode;
identify a die among a plurality of dies of the flash memory device that has a higher data occupancy than at least one other die among the plurality of dies of the flash memory device; and
send a second command and logical block addresses associated with data stored at the identified die to the flash memory device to move the data from the identified die to one or more other dies of the plurality of dies of the flash memory device, wherein the second command corresponds to a refresh operation of the flash memory device that causes the flash memory device to distribute the logical block addresses among the plurality of dies of the flash memory device.