US 12,346,584 B2
Read operations for mixed data
Scheheresade Virani, Frisco, TX (US); Raja V.S. Halaharivi, Gilroy, CA (US); and Ning Zhao, Milpitas, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 29, 2022, as Appl. No. 17/822,893.
Prior Publication US 2024/0069771 A1, Feb. 29, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory; and
one or more components configured to:
obtain, from a host device, a read command for reading data associated with a plurality of logical blocks;
read, from the memory, the data corresponding to the plurality of logical blocks;
encode the data corresponding to the plurality of logical blocks with a plurality of respective status indicators,
wherein the plurality of respective status indicators indicate memory statuses of the data stored in the plurality of logical blocks or of a plurality of physical addresses that are associated with the plurality of logical blocks;
provide, by a controller of the memory device to a hardware component of the one or more components of the memory device, a single data transfer request indicating the plurality of logical blocks encoded with the plurality of respective status indicators; and
provide, by the hardware component and to the host device, a plurality of responses to the read command based on the single data transfer request.