US 12,346,582 B2
Techniques for memory system rebuild
Giuseppe Cariello, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 17, 2022, as Appl. No. 17/663,800.
Prior Publication US 2023/0376225 A1, Nov. 23, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory system, comprising:
processing circuitry associated with one or more memory devices and configured to cause the memory system to:
determine a power on condition of the memory system;
read, based at least in part on determining the power on condition, metadata stored at a first physical address of the memory system, the metadata comprising an indication that one or more logical addresses for data stored prior to the power on condition at one or more physical addresses are sequential and a parameter indicating a quantity of the one or more physical addresses;
generate, based at least in part on reading the metadata, the one or more logical addresses based at least in part on the indication and the parameter; and
compress a portion of a mapping between logical addresses associated with the data and the one or more physical addresses associated with the data, the portion of the mapping comprising a subset of the one or more physical addresses, based at least in part on generating the one or more logical addresses and identifying that the subset comprises a first logical boundary and a second logical boundary of the memory system.