US 12,346,579 B2
On-demand activation of memory path during sleep or active modes
Daniel Martin Cermak, Austin, TX (US); Scott McLean Hanson, Morganville, NJ (US); Yousof Mortazavi, Austin, TX (US); and Ramakanth Kondagunturi, Austin, TX (US)
Assigned to Ambiq Micro, Inc., Austin, TX (US)
Filed by Ambiq Micro, Inc., Austin, TX (US)
Filed on Jul. 1, 2024, as Appl. No. 18/760,849.
Application 18/760,849 is a continuation of application No. 17/981,149, filed on Nov. 4, 2022, granted, now 12,050,789.
Application 17/981,149 is a continuation of application No. 17/747,410, filed on May 18, 2022, granted, now 11,520,499, issued on Dec. 6, 2022.
Prior Publication US 2024/0354012 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0626 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A low-power system-on-chip comprising:
an originating controller configured to initiate a memory transaction request, the memory transaction request including a source address;
an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request;
a fabric communicatively coupled to the originating controller and configured to perform a memory operation based on the memory transaction request; and
a power controller communicatively coupled to the arbiter and at least one of the originating controller or the fabric, the power controller configured to:
selectively change a second memory bank from a first power mode to a second power mode in response to the fabric performing the memory operation on a first memory bank of the first memory device;
wherein the fabric is configured to perform the memory operation by
(a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and
(b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program request or a write request.