US 12,346,578 B2
Distributed temperature sensing scheme to suppress peak Icc in non-volatile memories
Abu Naser Zainuddin, Milpitas, CA (US); Jiahui Yuan, Fremont, CA (US); and Sai Gautham Thoppa, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 26, 2023, as Appl. No. 18/359,025.
Claims priority of provisional application 63/510,334, filed on Jun. 26, 2023.
Prior Publication US 2024/0427502 A1, Dec. 26, 2024
Int. Cl. G11C 7/04 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 7/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory system, comprising:
a control circuit configured to connect to a first plane of non-volatile memory cells formed on a first die, the first die including one or more temperature sensors, including a first temperature sensor, each configured to provide a corresponding temperature value measured for the first plane during an access operation of the memory cells of the first plane, the control circuit configured to:
perform a first memory operation accessing the memory cells of the first plane;
while performing the first memory operation, receive the temperature values corresponding to the first temperature sensor;
while performing the first memory operation, determine an amount by which the received temperature values corresponding to the first temperature sensor has changed, including comparing the received temperature value corresponding to the first temperature sensor to a threshold value; and
alter, during the first memory operation, one or more bias conditions for performing the first memory operation based on the amount by which the received temperature values corresponding to the first temperature sensor has changed while performing the first memory operation.