US 12,346,574 B2
Enabling stripe-based operations for error recovery at a memory sub-system
Juane Li, Milpitas, CA (US); Fangfang Zhu, San Jose, CA (US); and Jiangli Zhu, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Aug. 31, 2023, as Appl. No. 18/459,286.
Application 18/459,286 is a continuation of application No. 17/459,927, filed on Aug. 27, 2021, granted, now 11,775,179.
Prior Publication US 2023/0409210 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/14 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0631 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 11/1435 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a stripe-based command pertaining to a set of host data items at management units (MUs) of a memory sub-system configured to support non-stripe based commands;
determining a set of operations to be executed at the MUs based on the stripe-based command, wherein the set of operations comprise one or more first operations associated with the set of host data items, the one or more first operations having a first operation type, and one or more second operations associated with the set of host data items, the one or more second operations having a second operation type;
executing a first set of commands corresponding to the one or more first operations of the set of operations; and
executing a second set of commands corresponding to the one or more second operations of the set of operations.