US 12,346,567 B2
Partial array refresh timing
Liji Gopalakrishnan, Sunnyvale, CA (US); Thomas Vogelsang, Mountain View, CA (US); and John Eric Linstadt, Palo Alto, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Nov. 27, 2023, as Appl. No. 18/519,359.
Application 18/519,359 is a continuation of application No. 17/785,269, granted, now 11,868,619, previously published as PCT/US2020/063135, filed on Dec. 3, 2020.
Claims priority of provisional application 62/951,953, filed on Dec. 20, 2019.
Prior Publication US 2024/0176497 A1, May 30, 2024
Int. Cl. G06F 3/06 (2006.01); G11C 11/406 (2006.01); G06F 13/16 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 11/40622 (2013.01); G06F 13/1636 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a command interface to couple to a memory component that includes a refresh masking register;
a shadow refresh masking register to store values corresponding to values currently stored by the refresh masking register of the memory component;
the command interface to transmit a first indicator of a first masked segment to the memory component;
shadow refresh masking register updating circuitry to, based on an indicator of the first masked segment, update the shadow refresh masking register to indicate a first masked segments value that indicates the first masked segment will not be refreshed by the memory component in response to a next refresh command transmitted via the command interface; and
command timing control circuitry to, based on the first masked segments value, select a first minimum required time interval between a first transmission, via the command interface, of the next refresh command and a second transmission, via the command interface, of a next subsequent non-refresh memory access command.