US 12,346,478 B2
Secure computation system, secure computation apparatus, method, and program
Atsunori Ichikawa, Tokyo (JP); and Koki Hamada, Tokyo (JP)
Assigned to NIPPON TELEGRAPH AND TELEPHONE CORPORATION, Tokyo (JP)
Appl. No. 18/552,075
Filed by NIPPON TELEGRAPH AND TELEPHONE CORPORATION, Tokyo (JP)
PCT Filed Apr. 19, 2021, PCT No. PCT/JP2021/015927
§ 371(c)(1), (2) Date Sep. 22, 2023,
PCT Pub. No. WO2022/224319, PCT Pub. Date Oct. 27, 2022.
Prior Publication US 2024/0176908 A1, May 30, 2024
Int. Cl. G06F 21/62 (2013.01); G06F 7/58 (2006.01)
CPC G06F 21/6245 (2013.01) [G06F 7/582 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A secure computation system including a first secure computation apparatus, a second secure computation apparatus, and a third secure computation apparatus each having a tripartite share of a concealed input vector,
wherein the first secure computation apparatus includes
a processor; and
a memory storing program instructions that cause the processor to:
convert its own tripartite share into a bipartite share with the third secure computation apparatus;
calculate a third vector obtained by subtracting, from a result of applying its own permutation to its own bipartite share, a result of applying a second permutation determined according to the permutation to a first vector determined by a predetermined method and a second vector determined by a predetermined method; and
transmit the third vector and the second permutation to the second secure computation apparatus,
the third secure computation apparatus includes
a processor; and
a memory storing program instructions that cause the processor to
convert its own tripartite share into a bipartite share with the first secure computation apparatus;
calculate a fourth vector obtained by adding the first vector to a result of applying a first permutation determined according to the permutation to its own bipartite share;
transmit the fourth vector to the third secure computation apparatus;
set the second vector as a bipartite share, with the second secure computation apparatus, of a result of applying the permutation to the input vector, and
the second secure computation apparatus includes
a processor; and
a memory storing program instructions that cause the processor to set a vector obtained by adding a result of applying the second permutation to the fourth vector to the third vector, as a bipartite share, with the third secure computation apparatus, of the result of applying the permutation to the input vector.