| CPC G06F 13/4031 (2013.01) [G06F 11/1004 (2013.01); H04J 3/02 (2013.01)] | 30 Claims |

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11. A method implemented using integrated circuitry, the integrated circuitry comprising configuration selection circuitry and receive datapath circuitry, the method comprising:
generating, by the configuration selection circuitry, one or more input signals to be provided to the receive datapath circuitry, the receive datapath circuitry being configurable to implement multiple receive datapath configurations between, at least in part, receive Media Access Control (MAC) layer processing circuitry and receive PHY layer processing circuitry, the multiple receive datapath configurations being mutually different from each other, at least in part, the one or more input signals to be provided to the receive datapath circuitry to select which of the multiple receive datapath configurations the receive datapath circuitry is to implement;
wherein:
the multiple receive datapath configurations are associated with respective datapath widths, respective supported link speeds, and respective supported lane configurations;
the respective datapath widths comprise an 8 byte datapath width;
the respective supported link speeds comprise 100 gigabit (Gb)/second(s), 200 Gb/s, 400 Gb/s, and one or more other link speeds; and
the respective supported lane configurations comprise 1 lane/link, 2 lanes/link, 4 lanes/link, and at least one other number of lanes/link.
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