US 12,346,265 B2
Cache line re-reference interval prediction using physical page address
Jieming Yin, Bothell, WA (US); Yasuko Eckert, Redmond, WA (US); and Subhash Sethumurugan, Minneapolis, MN (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 16, 2019, as Appl. No. 16/716,165.
Prior Publication US 2021/0182213 A1, Jun. 17, 2021
Int. Cl. G06F 12/122 (2016.01)
CPC G06F 12/122 (2013.01) [G06F 2212/1021 (2013.01); G06F 2212/1044 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a cache configured to store a plurality of cache lines; and
a cache controller; wherein responsive to allocating an entry in the cache for a first cache line corresponding to a page, the cache controller comprises circuitry configured to:
store the first cache line in the cache; and
set a re-reference prediction value (RRPV) for the first cache line to an initial value, wherein the initial value is based at least in part on a previous access to a second cache line that corresponds to the page, wherein the RRPV for the first cache line is distinct from an RRPV of the second cache line.