US 12,346,259 B1
Cache resource prioritization for heterogeneous multi-processing (HMP) architecture
Aiqun Yu, Shanghai (CN); Yiwei Huang, Shanghai (CN); and Junwei Liao, Shanghai (CN)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Apr. 15, 2024, as Appl. No. 18/635,389.
Int. Cl. G06F 12/0811 (2016.01); G06F 12/0871 (2016.01)
CPC G06F 12/0871 (2013.01) [G06F 12/0811 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of Heterogeneous Multi-Processing (HMP) cores having different levels of processing capability;
a cache including cache partitions assigned to the different levels of the HMP cores;
a performance monitoring unit (PMU) configured to track a performance attribute for each of the cache partitions; and
a controller configured, for each of a plurality of successive time windows, to:
obtain a performance value for each of the cache partitions based on the performance attribute tracked by the PMU;
determine a predicted cache size for each of the cache partitions based on performance values obtained for a previous N successive time windows, wherein N is an integer greater than one;
calculate a cache size for each of the cache partitions by multiplying the predicted cache size with a weighted value, wherein the weighted value is larger for a cache partition associated with a HMP core having higher processing capability; and
direct a size adjustment of each of the cache partitions based on the calculated cache size.