US 12,346,254 B2
High-performance computing system
Romain Dolbeau, Rennes (FR)
Assigned to SIPEARL, Maisons-Lafitte (FR)
Appl. No. 18/018,801
Filed by SIPEARL, Maisons-Laffitte (FR)
PCT Filed Jul. 29, 2021, PCT No. PCT/EP2021/071342
§ 371(c)(1), (2) Date Jan. 30, 2023,
PCT Pub. No. WO2022/023500, PCT Pub. Date Feb. 3, 2022.
Claims priority of application No. 20188737 (EP), filed on Jul. 30, 2020.
Prior Publication US 2023/0325315 A1, Oct. 12, 2023
Int. Cl. G06F 12/0813 (2016.01); G06F 12/0815 (2016.01); G06F 15/173 (2006.01)
CPC G06F 12/0813 (2013.01) [G06F 12/0815 (2013.01); G06F 15/17368 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A high-performance computing system that processes data and performs complex calculations at, at least, tera calculations per second, comprises:
at least one computational group of at least one core, each computational group being associated with a computational memory, arranged to form a computational resource being utilized for performing computations, said computational memory being a high bandwidth memory or a hybrid memory cube or a double data rate synchronous dynamic random-access memory;
a concierge module comprising at least one concierge group of at least one core associated with a concierge memory arranged to form a reserved support resource being utilized for performing support functions to said computational resource, said concierge memory being a double data rate synchronous dynamic random-access memory or a high bandwidth memory or a hybrid memory cube, wherein support functions comprises operating system, In/Out connections functions, and software and user applications monitoring;
wherein the computational resource is coupled to the concierge module through a cache coherent interconnection to maintain uniformity of shared resource data that are stored in the computational memory and concierge memory,
wherein the, at least one, core in the, at least one, computational group and the, at least one, core in the, at least one, concierge group are interchangeable for software codes such that said cores are used for performing any one of computations or support functions, and said cores use any one of the computational memory and concierge memory, and
wherein accesses to the computational memory and to the concierge memory are not homogeneous, in terms of performances, across the cores of the computational group relative to the cores of the concierge group.