US 12,346,235 B2
Semiconductor chip, debug system, and synchronization method
Hiroyuki Sasaki, Tokyo (JP); and Hirofumi Hatahara, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Oct. 6, 2023, as Appl. No. 18/482,241.
Claims priority of application No. 2022-185608 (JP), filed on Nov. 21, 2022.
Prior Publication US 2024/0168861 A1, May 23, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 11/32 (2006.01); G06F 11/34 (2006.01)
CPC G06F 11/348 (2013.01) [G06F 11/323 (2013.01); G06F 11/3476 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor chip comprising:
a first common marker generating circuit configured to send a common marker to a first trace memory, the first trace memory being configured to store trace data from a first core and the common marker; and
a second common marker generating circuit configured to send the common marker to a second trace memory, the second trace memory being configured to store trace data from a second core and the common marker, the second core being different from the first core,
wherein the common marker allows synchronization between the trace data from the first core with the trace data from the second core,
wherein the first common marker generating circuit is configured to send, to the second common marker generating circuit, a first request signal while the first core is running a first user program, the first request signal requesting the second common marker generating circuit to send the common marker to the second trace memory,
wherein, upon receiving the first request signal from the first common marker generating circuit while the second core is running a second user program, the second common marker generating circuit is configured to i) send the common marker to the second trace memory and ii) send a second request signal to the first common marker generating circuit, the second request signal requesting the first common marker generating circuit to send the common marker to the second trace memory, and
wherein, upon receiving the second request signal from the second common marker generating circuit, the first common marker generating circuit is configured to send the common marker to the first trace memory.