US 12,346,184 B2
Reduced common mode voltage pulse width modulation switching scheme with capacitor voltage balancing for a multilevel power converter
Kum Kang Huh, Niskayuna, NY (US); Hridya Ittamveettil, Bengaluru (IN); Luis J. Garces, Niskayuna, NY (US); Rajib Datta, Niskayuna, NY (US); Di Pan, Schenectady, NY (US); and Yukai Wang, Schenectady, NY (US)
Assigned to General Electric Company, Evendale, OH (US)
Filed by General Electric Company, Schenectady, NY (US)
Filed on Apr. 26, 2023, as Appl. No. 18/307,375.
Claims priority of application No. 202311003782 (IN), filed on Jan. 19, 2023.
Prior Publication US 2024/0248522 A1, Jul. 25, 2024
Int. Cl. G06F 1/00 (2006.01); B64D 41/00 (2006.01); G06F 1/30 (2006.01); H02M 1/00 (2006.01); H02M 7/797 (2006.01); G06F 1/3203 (2019.01)
CPC G06F 1/30 (2013.01) [B64D 41/00 (2013.01); H02M 1/0043 (2021.05); H02M 7/797 (2013.01); G06F 1/3203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multilevel power converter for an aircraft, comprising:
a plurality of switches;
a first direct current (DC) link capacitor;
a second DC link capacitor; and
one or more processors configured to:
generate, for a duty cycle of the multilevel power converter, a pulse width modulated pulse pattern in accordance with a reduced common mode voltage scheme;
modify the pulse width modulated pulse pattern to render a modified pulse pattern by delaying in time or advancing in time at least one of a falling edge or a rising edge of a pulse of a pulse width modulated signal of the pulse width modulated pulse pattern; and
cause the plurality of switches to implement the duty cycle based at least in part on the modified pulse pattern to render a common mode voltage pulse to balance a first voltage at the first DC link capacitor with a second voltage at the second DC link capacitor.