US 12,346,148 B2
Digital clock signal generator, chip, and method for generating spread-spectrum synchronous clock signals
Xiangye Wei, Beijing (CN); and Liming Xiu, Beijing (CN)
Assigned to Beijing BOE Technology Development Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by Beijing BOE Technology Development Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Aug. 31, 2023, as Appl. No. 18/459,053.
Application 18/459,053 is a continuation in part of application No. 16/975,258, granted, now 11,848,679, previously published as PCT/CN2019/110152, filed on Oct. 9, 2019.
Prior Publication US 2023/0409074 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03D 3/24 (2006.01); G06F 1/08 (2006.01)
CPC G06F 1/08 (2013.01) 19 Claims
OG exemplary drawing
 
1. A method for generating spread-spectrum synchronous clock signals comprising:
comparing an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback;
generating a first control signal and a second control signal;
determining an integer part I of a control word F to track the first frequency;
registering n levels for the first control signal and the second control signal to introduce n phase delays for randomly changing a fraction part r (0<r<1) of the control word F to provide a broadened boundary in frequency spectrum; and
generating a synthesized periodic signal with the second frequency based on a base time unit Δ, the first frequency, and the control word F, the synthesized periodic signal being fed back as the feedback signal in the loop of feedback and outputted with the second frequency being locked within the broadened boundary of the first frequency.