US 12,346,147 B2
Circuit and methodology for power profile
Sandeep Goel, Dublin, CA (US); Ankita Patidar, San Jose, CA (US); and Yun-Han Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 3, 2023, as Appl. No. 18/365,006.
Prior Publication US 2025/0044825 A1, Feb. 6, 2025
Int. Cl. G06F 1/08 (2006.01); G06F 1/12 (2006.01)
CPC G06F 1/08 (2013.01) 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal, and to generate a first fast clock enable signal and a first slow clock enable signal,
wherein the on-chip clock controller is configured to override the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal and to override the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal, and
wherein the on-chip clock controller includes a first clock circuit and a second clock circuit, wherein the first clock circuit includes a first AND gate having a first non-inverted input that receives the mode signal and a second non-inverted input that receives the speed enable signal, and a second AND gate having a third non-inverted input that receives the mode signal and an inverted input that receives the speed enable signal, wherein the first AND gate provides a first AND gate output signal and the second AND gate provides a second AND gate output signal.