US 12,345,932 B2
Die last and waveguide last architecture for silicon photonic packaging
Bai Nie, Chandler, AZ (US); Pooya Tadayon, Portland, OR (US); Leonel R. Arana, Phoenix, AZ (US); Yonggang Li, Chandler, AZ (US); Changhua Liu, Chandler, AZ (US); Kristof Darmawikarta, Chandler, AZ (US); Srinivas Venkata Ramanuja Pietambaram, Chandler, AZ (US); Tarek A. Ibrahim, Mesa, AZ (US); Hari Mahalingam, San Jose, CA (US); and Benjamin Duong, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2021, as Appl. No. 17/483,013.
Prior Publication US 2023/0087124 A1, Mar. 23, 2023
Int. Cl. G02B 6/42 (2006.01); G02B 6/43 (2006.01)
CPC G02B 6/4243 (2013.01) [G02B 6/43 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor assembly comprising:
a first glass substrate;
an electronic integrated circuit (“EIC”);
a photonic integrated circuit (“PIC”) configured to produce an optical frequency, the PIC comprising an optical port;
a bridge die connecting the PIC and the EIC, wherein the bridge die is embedded in the first glass substrate; and
a coupling adapter, bonded to the first glass substrate, comprising:
a coupling port configured for connecting to an optical fiber; and
a waveguide integrated with the coupling adapter.