US 12,345,794 B2
Distributed clock system for the synchronization of instrumentation
Blake J. Landry, Saint Martinville, LA (US); and Charles R. Key, Diamondhead, MS (US)
Assigned to The Government of the United States of America, as represented by the Secretary of the Navy, Arlington, VA (US)
Filed by The Government of the United States of America, as represented by the Secretary of the Navy, Arlington, VA (US)
Filed on Oct. 1, 2021, as Appl. No. 17/491,902.
Claims priority of provisional application 63/086,761, filed on Oct. 2, 2020.
Prior Publication US 2022/0107401 A1, Apr. 7, 2022
Int. Cl. G01S 11/08 (2006.01); G01S 19/24 (2010.01); G01S 19/39 (2010.01); G04G 5/00 (2013.01); G04G 7/00 (2006.01); G04R 20/02 (2013.01)
CPC G01S 11/08 (2013.01) [G01S 19/24 (2013.01); G01S 19/39 (2013.01); G04G 5/00 (2013.01); G04G 7/00 (2013.01); G04R 20/02 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, by a Global Positioning System (GPS) timing receiving circuit of a distributed clock system (DCS) device, a GPS signal from a GPS source, the GPS signal indicating time including a current time, the GPS signal alternating between a low value and a high value, wherein the GPS signal has a frequency lower than a frequency of a raw clock signal;
determining, by the GPS timing receiving circuit and based on the received GPS signal, that a first current time equals a predetermined start time;
generating, by the GPS timing receiving circuit, a shifted GPS signal by applying a configurable delay to the received GPS signal, the shifted GPS signal alternating between a low value and a high value;
responsive to a falling edge of the shifted GPS signal, generating, by an arming circuit of the DCS device, an ARM signal having a rising edge after the falling edge of the shifted GPS signal;
responsive to the ARM signal being high and the shifted GPS signal being high, generating, by an output enabling circuit of the DCS device, an output enable signal; and
transmitting, by a generator circuit of the DCS device, while the output enable signal is high, a triggering signal to one or more sampling devices, the triggering signal comprising one or more synchronizing pulses that cause the one or more sampling devices to sample data according to the frequency of the raw clock signal.