US 12,345,757 B2
Decoupling cells testability
Ido Bourstein, Pardes Hanna-Karkur (IL); and Idan Avni, Haifa (IL)
Assigned to Mellanox Technologies, Ltd, Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on May 1, 2023, as Appl. No. 18/309,841.
Prior Publication US 2024/0369619 A1, Nov. 7, 2024
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2853 (2013.01) [G01R 31/2884 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising one or more testable voltage decoupling (DCAP) cells, each of the testable DCAP cells comprising:
one or more decoupling capacitors connected between supply rails of the IC; and
a decoupling-test active logic (DTAL) circuit, wherein the DTAL circuit comprises an inverter or an active buffer; wherein the inverter or the active buffer, which has a normal input-output response, is configured to deviate from the normal input-output response in response to a fault in the DCAP cell.