US 12,345,747 B2
In memory computing (IMC) memory device and method
Yu-Yu Lin, New Taipei (TW); and Feng-Min Lee, Hsinchu (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Dec. 29, 2022, as Appl. No. 18/147,727.
Prior Publication US 2024/0219437 A1, Jul. 4, 2024
Int. Cl. G01R 19/257 (2006.01); G01R 19/00 (2006.01)
CPC G01R 19/257 (2013.01) [G01R 19/0023 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An in-memory computing (IMC) memory device including:
a plurality of memory cells, the memory cells forming a plurality of computing layers; and
a plurality of computing layer connectors, the computing layer connectors connecting between the computing layers,
wherein,
a first computing layer input is inputted into a first computing layer of the computing layers, the first computing layer generates a first computing layer output,
a first computing layer connector of the computing layer connectors converts the first computing layer output into a second computing layer input, the first computing layer connector inputs the second computing layer input into a second computing layer of the computing layers, and
the computing layer connectors are a plurality of inverters,
wherein the first computing layer connector is one inverter among the plurality of inverters, the first computing layer connector includes a first transistor and a second transistor, control terminals of the first and the second transistors receive the first computing layer output, first terminals of the first and the second transistor generate the second computing layer input, a device driving ratio of the first and the second transistors of the first computing layer connector is adjusted to change a switching threshold voltage position of the first computing layer connector,
the first computing layer input controls resistance of the memory cells of the first computing layer;
a plurality of driving currents are applied to the memory cells of the first computing layer via a plurality of bit lines; and
the first computing layer output is a computation result of the plurality of driving currents with voltage drops of the memory cells of the first computing layer.