forming a light shielding layer on a substrate;

coating a transparent metal oxide onto the substrate and the light shielding layer, and patterning the transparent metal oxide to form a first conductive layer, wherein one end of the first conductive layer is overlapped with the light shielding layer;

sequentially depositing a buffer layer, a semiconductor layer, a first insulating layer, and a first metal layer on the substrate, and patterning the semiconductor layer, the first insulating layer, and the first metal layer to form a first semiconductor layer, a second semiconductor layer, a gate insulating layer, and a gate, wherein the first semiconductor layer and the second semiconductor layer are spaced apart from each other;

by using the gate and the gate insulating layer as a shield, performing plasma treatment on the first semiconductor layer and the second semiconductor layer to obtain an active layer and a second conductive layer spaced apart from the active layer;

forming a second insulating layer which covers the buffer layer, the active layer, the second conductive layer, the gate insulating layer, the gate insulating layer, and the gate, and patterning the second insulating layer and the buffer layer to form a first via hole which exposes the active layer, a second via hole which exposes the active layer, and a third via hole which exposes the light shielding layer;

forming a second metal layer on the second insulating layer, and patterning the second metal layer to form a source and a drain, wherein the drain is connected to the active layer through the first via hole, the source is connected to the active layer through the second via hole, and the source is connected to the light shielding layer through the third via hole;

forming a passivation layer covering the second insulating layer, the source, and the drain;

forming a planarization layer covering the passivation layer, and patterning the passivation layer and the planarization layer to form a fourth via hole which exposes the source and to form an opening which exposes the second insulating layer;

coating the planarization layer and the opening with a transparent metal oxide, and patterning the transparent metal oxide to form a pixel electrode, wherein the pixel electrode is connected to the source through the fourth via hole; and

forming a pixel definition layer covering the planarization layer and the pixel electrode, and patterning the pixel definition layer to expose the pixel electrode located above the opening,

wherein the first conductive layer, the buffer layer, the second conductive layer, the second insulating layer, and the pixel electrode constitute a three-layer transparent capacitor structure,

wherein the opening is completely filled with the pixel electrode and penetrates the passivation layer and the planarization layer, and the opening is arranged corresponding to the three-layer transparent capacitor structure.