| CPC H10B 43/27 (2023.02) [H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/7684 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02); H01L 2221/1063 (2013.01)] | 18 Claims |
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1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a channel structure extending vertically through a dielectric stack comprising interleaved sacrificial layers and dielectric layers above a substrate, wherein the channel structure comprises a channel plug;
forming a sacrificial plug above and in contact with the channel structure;
forming a slit opening extending vertically through the dielectric stack;
forming a memory stack comprising interleaved conductive layers and the dielectric layers by replacing, through the slit opening, the sacrificial layers with the conductive layers;
forming a first contact portion in the slit opening;
removing the sacrificial plug after forming the first contact portion to expose the channel structure; and
simultaneously forming (i) a channel local contact above and in contact with the channel structure, and (ii) a second contact portion in the slit opening, wherein a bottom surface of the second contact portion is above and in contact with a top surface of the first contact portion,
wherein forming the channel structure comprises: etching a channel hole extending vertically through the dielectric stack;
subsequently forming a memory film and a semiconductor channel over a sidewall of the channel hole; and
forming the channel plug above and in contact with the semiconductor channel;
wherein forming the sacrificial plug comprises:
forming a local dielectric layer on the dielectric stack;
etching a local contact hole through the local dielectric layer to expose the channel structure; and
depositing a sacrificial material that is different from a material of the channel plug into the local contact hole.
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