US 12,021,986 B2
Neural network processing method and server and electrical device therefor
Ming-Chih Tung, Taoyuan (TW); Hsin-Lung Wu, Taoyuan (TW); Juin-Ming Lu, Hsinchu (TW); and Bo-Xuan Zhu, New Taipei (TW)
Assigned to INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Hsinchu (TW)
Filed by INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Hsinchu (TW)
Filed on Dec. 27, 2021, as Appl. No. 17/562,700.
Prior Publication US 2023/0208639 A1, Jun. 29, 2023
Int. Cl. H04L 9/32 (2006.01); G06F 8/41 (2018.01); G06N 3/063 (2023.01)
CPC H04L 9/32 (2013.01) [G06F 8/41 (2013.01); G06N 3/063 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neural network (NN) processing method, comprising:
transforming an AI (artificial intelligence) compiler code of an AI compiler to a garbled circuit code by performing following steps:
sending a circuit graph of a garbled circuit corresponding to the garbled circuit code to a first electrical device by a server, the garbled circuit having a plurality of logic gates;
creating a plurality of key codebooks for a plurality of candidate gates corresponding to each logic gate by the first electrical device;
generating a plurality of garbled truth tables for the candidate gates corresponding to each logic gate by the first electrical device;
transmitting the garbled truth tables for the candidate gates corresponding to each logic gate to the server by the first electrical device through using OT (Oblivious Transfer) protocol; and
obtaining a target garbled truth table of each logic gate through using OT protocol based on the garbled truth tables for the candidate gates corresponding to each logic gate by the server;
encrypting an NN model according to the key codebooks by the first electrical device; and
generating a compiled NN model of an encrypted NN model according to the garbled circuit code with the target garbled truth table of each logic gate by the server.