US 12,021,611 B2
Synchronizing systems-on-chip using GPIO timestamps
Samuel Ahn, Marina Del Rey, CA (US); Dmitry Ryuma, Sherman Oaks, CA (US); and Richard Zhuang, San Diego, CA (US)
Assigned to Snap Inc., Santa Monica, CA (US)
Filed by Samuel Ahn, Marina Del Rey, CA (US); Dmitry Ryuma, Sherman Oaks, CA (US); and Richard Zhuang, San Diego, CA (US)
Filed on Oct. 7, 2021, as Appl. No. 17/496,261.
Prior Publication US 2023/0113076 A1, Apr. 13, 2023
Int. Cl. H04W 56/00 (2009.01); G02B 27/01 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); G06F 13/24 (2006.01); G06F 13/40 (2006.01); H04J 3/06 (2006.01)
CPC H04J 3/065 (2013.01) [G02B 27/017 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); G06F 13/24 (2013.01); G06F 13/4068 (2013.01); G02B 2027/0178 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/0038 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of synchronizing first and second systems-on-chip (SoCs) of an electronic eyewear device, the first and second SoCs having independent time bases, the method comprising:
(a) the first SoC asserting a shared general purpose input/output (GPIO) connection to the second SoC, assertion of the shared GPIO connection triggering an interrupt request (IRQ) at the second SoC;
(b) the first SoC recording a first timestamp for a time of assertion of the shared GPIO connection;
(c) the second SoC recording a second timestamp of receipt of the IRQ on the shared GPIO connection;
(d) the first SoC sending a message including the first timestamp to the second SoC over an inter-SoC interface;
(e) the second SoC calculating a clock offset between the first SoC and the second SoC as a difference between the first timestamp and the second timestamp; and
(f) the second SoC calculating a clock of the first SoC as a sum of the local timestamp and the calculated clock offset.