a first plurality of driver circuits configured to generate, on a first signal line included in a communication bus and based on a plurality of bits, a first subset of a plurality of voltage levels;

a second plurality of driver circuits configured to generate on a second signal line included in the communication bus and based on the plurality of bits, a second subset of the plurality of voltage levels, wherein a data symbol based on respective values of the plurality of bits is encoded using respective voltage levels of the first signal line and the second signal line; and

a shunt circuit configured to couple the first signal line to the second signal line in response to a determination that a subset of the plurality of bits matches a particular pattern.