| CPC H03K 19/0813 (2013.01) [H03K 19/018585 (2013.01); H03K 19/17784 (2013.01); H03K 19/20 (2013.01)] | 15 Claims |
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1. A mixed signal device comprising of at least a plurality of digital logic cells, comprising:
a first plurality of digital logic cells being directly connected to a Vdd terminal and a Vss terminal, wherein a potential difference between the Vdd terminal and Vss terminal is a VDD;
a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD−X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein X1 and X2 are positive voltages and X1 and X2 both are less than half of the VDD;
wherein at least one digital logic cell of the first plurality of digital logic cells has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality;
wherein a first ratio of the voltage X1 to the voltage X2 is selected in a preselected range; and
a storage digital logic cell, wherein the storage digital logic cell comprises at least one digital logic cell of the first plurality of digital logic cells and at least one digital logic cell of the second plurality of digital logic cells, and wherein the at least one digital logic cell of the first plurality of digital logic cells is configured to be in a feedforward path from an input of the storage digital logic cell to an output of the storage digital logic cell and the at least one digital logic cell of the second plurality of digital logic cells is configured to be in a feedback path from an output to an input of the storage digital logic cell.
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