| CPC H01L 29/42352 (2013.01) [H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42328 (2013.01); H01L 29/42336 (2013.01); H01L 29/42344 (2013.01); H01L 29/66545 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 7 Claims |
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1. A semiconductor device, comprising:
a first stack of alternating insulating layers and word line layers over a substrate, the first stack including a core region and a staircase region, and the word line layers including a TSG;
first channel structures in the core region of the first stack, the first channel structures extending through the core region of the first stack and including a channel layer surrounded by one or more insulating layers;
a first TSG cut structure in the core region and a second TSG cut structure in the staircase region, the first TSG cut structure being adjacent to and connected with the second TSG cut structure, both the first TSG cut structure and the second TSG cut structure extending through the TSG and dividing the TSG into sub-TSGs; and
dummy channel structures that extend through the first stack,
wherein both the first TSG cut structure and the second TSG cut structure extend through at least one pair of alternating insulating layers and word line layers to divide the TSG.
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