US 12,021,126 B2
Method of forming top select gate trenches
Hang Yin, Wuhan (CN); Zhipeng Wu, Wuhan (CN); Kai Han, Wuhan (CN); Lu Zhang, Wuhan (CN); Pan Wang, Wuhan (CN); Xiangning Wang, Wuhan (CN); Hui Zhang, Wuhan (CN); Jingjing Geng, Wuhan (CN); and Meng Xiao, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Dec. 23, 2020, as Appl. No. 17/132,802.
Application 17/132,802 is a continuation of application No. PCT/CN2020/114795, filed on Sep. 11, 2020.
Prior Publication US 2022/0085181 A1, Mar. 17, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H01L 29/42352 (2013.01) [H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42328 (2013.01); H01L 29/42336 (2013.01); H01L 29/42344 (2013.01); H01L 29/66545 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first stack of alternating insulating layers and word line layers over a substrate, the first stack including a core region and a staircase region, and the word line layers including a TSG;
first channel structures in the core region of the first stack, the first channel structures extending through the core region of the first stack and including a channel layer surrounded by one or more insulating layers;
a first TSG cut structure in the core region and a second TSG cut structure in the staircase region, the first TSG cut structure being adjacent to and connected with the second TSG cut structure, both the first TSG cut structure and the second TSG cut structure extending through the TSG and dividing the TSG into sub-TSGs; and
dummy channel structures that extend through the first stack,
wherein both the first TSG cut structure and the second TSG cut structure extend through at least one pair of alternating insulating layers and word line layers to divide the TSG.